US 12,283,324 B2
Array dependent voltage compensation in a memory device
Ke Zhang, Shanghai (CN); Liang Li, Shanghai (CN); and Ming Wang, Shanghai (CN)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jun. 10, 2022, as Appl. No. 17/838,004.
Prior Publication US 2023/0402099 A1, Dec. 14, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G11C 16/10 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a die including a CMOS wafer that includes programming and erasing circuitry;
a plurality of array wafers coupled with and in electrical communication with the CMOS wafer, the plurality of array wafers including memory blocks with memory cells;
the plurality of array wafers including a first array wafer that is bonded with the CMOS layer and a second array wafer that is bonded with the first array wafer on an opposite side of the first array wafer from the CMOS layer, the first array wafer having high programming and erasing efficiencies, and the second array wafer having low programming and erasing efficiencies; and
the programming and erasing circuitry of the CMOS wafer being configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.