| CPC G11C 16/0433 (2013.01) [G11C 16/102 (2013.01); G11C 16/3459 (2013.01)] | 18 Claims |
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1. A method of programming a memory device, the memory device comprising a plurality of memory strings, each memory string comprising a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and a plurality of memory cells between the top transistor and the bottom transistor, each memory cell connected to a word line (WL), the method comprising:
applying a plurality of program pulses to a memory cell of the memory device in a program phase;
verifying a voltage value of the memory cell in a verify phase;
receiving a suspend command and performing a suspend operation in response to the suspend command;
applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein applying the discharge pulse comprises applying:
a first voltage pulse to an unselected top select gate (TSGunsel), the first voltage pulse weighted to a first turn-on voltage VON1 of the TSGunsel;
a second voltage pulse to a selected top select gate (TSGsel), the second voltage pulse weighted to a second turn-on voltage Vtsg of the TSGsel;
a third voltage pulse to a bottom select gate (BSG), the third voltage pulse weighted to a third turn-on voltage VON2 of the BSG;
a fourth voltage pulse to an unselected word line (WLunsel), the fourth voltage pulse weighted to a first pass voltage VPASS1 of the WLunsel; and
a fifth voltage pulse to a selected word line (WLsel), the fifth voltage pulse weighted to a second pass voltage VPASS2 of the WLunsel; and
suspending programming or verifying of the memory cell in a suspend phase.
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