US 12,283,320 B2
Data processing method based on memristor array and electronic apparatus
Huaqiang Wu, Beijing (CN); Zhengwu Liu, Beijing (CN); Jianshi Tang, Beijing (CN); Bin Gao, Beijing (CN); and He Qian, Beijing (CN)
Assigned to TSINGHUA UNIVERSITY, Beijing (CN)
Appl. No. 17/788,408
Filed by TSINGHUA UNIVERSITY, Beijing (CN)
PCT Filed Dec. 14, 2021, PCT No. PCT/CN2021/137845
§ 371(c)(1), (2) Date Jun. 23, 2022,
PCT Pub. No. WO2022/222498, PCT Pub. Date Oct. 27, 2022.
Claims priority of application No. 202110426351.9 (CN), filed on Apr. 20, 2021.
Prior Publication US 2024/0170060 A1, May 23, 2024
Int. Cl. G06N 3/063 (2023.01); G06F 17/15 (2006.01); G06F 17/16 (2006.01); G06N 3/09 (2023.01); G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G06F 17/15 (2013.01); G06F 17/16 (2013.01); G06N 3/063 (2013.01); G06N 3/09 (2023.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 2213/79 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing method based on a memristor array, wherein the memristor array comprises a plurality of memristor units arranged in an array, and the memristor array is configured to perform a multiply-accumulate operation, the method comprises:
acquiring a plurality of first analog signals;
setting the memristor array, and writing data corresponding to a convolution parameter matrix of a convolution processing into the memristor array, wherein the convolution parameter matrix is a first matrix and comprises a plurality of parameter elements arranged in an array, the plurality of parameter elements are correspondingly mapped to a plurality of memristor sub-arrays in the memristor array for a plurality of times in a form of the first matrix, and the plurality of memristor sub-arrays are different, for any memristor unit in any memristor sub-array among the plurality of memristor sub-arrays, the any memristor unit is only comprised in the any memristor sub-array but not comprised in any other memristor sub-arrays among the plurality of memristor sub-arrays; and
inputting the plurality of first analog signals respectively into a plurality of column signal input terminals of the memristor array that has been set, controlling operation of the memristor array to perform the convolution processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the convolution processing at a plurality of row signal output terminals of the memristor array, respectively.