US 12,283,319 B2
Operating circuit and operating method of resistive random access memory
Peng Huang, Beijing (CN); Yizhou Zhang, Beijing (CN); Yulin Feng, Beijing (CN); Jinfeng Kang, Beijing (CN); Xiaoyan Liu, Beijing (CN); and Lifeng Liu, Beijing (CN)
Assigned to PEKING UNIVERSITY, Beijing (CN)
Appl. No. 17/631,611
Filed by Peking University, Beijing (CN)
PCT Filed Aug. 2, 2019, PCT No. PCT/CN2019/099061
§ 371(c)(1), (2) Date Jan. 31, 2022,
PCT Pub. No. WO2021/022410, PCT Pub. Date Feb. 11, 2021.
Prior Publication US 2022/0277791 A1, Sep. 1, 2022
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) 4 Claims
OG exemplary drawing
 
1. An operating method of a resistive random-access memory, wherein the method comprises:
connecting at least one capacitance in series with a resistive random-access memory, so that the resistive random-access memory is grounded through the at least one capacitance;
applying a forming pulse voltage or a set pulse voltage on the resistive random-access memory to achieve a forming operation or a set operation of the resistive random-access memory,
wherein the resistive random-access memory comprises an m×n resistive random-access memory array structure, each of m and n is a natural number greater than or equal to 1, top electrode terminals of a plurality of resistive random-access memory cells are connected to the same bit line in a column direction, and bottom electrode terminals of the plurality of resistive random-access memory cells are connected to the same word line in a row direction;
wherein the connecting at least one capacitance in series with a resistive random-access memory comprises connecting one capacitance on each word line, so that bottom electrode terminals of the plurality of resistive random-access memory cells connected to the same word line are grounded through the one capacitance; and
wherein the forming pulse voltages or the set pulse voltages are applied to the bit lines connected to the top electrode terminals of the plurality of resistive random-access memory cells,
wherein the resistive random-access memory comprises an m×n resistive random-access memory array structure, each of m and n is a natural number greater than or equal to 1, top electrode terminals of a plurality of resistive random-access memory cells are connected to the same bit line in a column direction, and bottom electrode terminals of the plurality of resistive random-access memory cells are connected to the same word line in a row direction, line resistances of the word line between any two adjacent resistive random-access memory cells are Rwire and line capacitances of the word line between any two adjacent resistive random-access memory cells are Cwire, each of the line capacitances is connected in parallel, and an influence of the line capacitances is considered to be grounded through one capacitance of n×Cwire on the word line;
wherein the connecting at least one capacitance in series with a resistive random-access memory comprises using the line capacitances connected in parallel as grounded capacitances;
wherein the forming pulse voltages or the set pulse voltages are applied to the bit lines connected to the top electrode terminals of the plurality of resistive random-access memory cells,
wherein the forming pulse voltages are applied to the bit lines connected to the top electrode terminals of the plurality of resistive random-access memory cells comprises:
selecting a first row bit line BL1 through a bit line terminal MUX, floating a word line terminal MUX, so that the word lines WL1, WL2, . . . , WLm for each column are grounded through the capacitances; applying a forming pulse voltage with a certain duration to the first row bit line BL1, so as to complete a forming process of m resistive random-access memory cells connected to the first row bit line BL1;
turning on and grounding the word line terminal MUX, and resetting voltages on the capacitances to 0 after the forming process of the m resistive random-access memory cells connected to the first row bit line BL1 is completed; after that, turning off the word line terminal MUX, and selecting a second row bit line BL2 through the bit line terminal MUX, applying a forming pulse voltage with a certain duration to the second row bit line BL2, so as to complete a forming process of m resistive random-access memory cells connected to the second row bit line BL2;
repeating the above process until a forming process of m resistive random-access memory cells connected to a nu row bit line BLn is completed, so that a forming process of the entire resistive random-access memory array is completed.