US 12,283,318 B2
Matching patterns in memory arrays
Dmitri Yudanov, Sacramento, CA (US)
Assigned to Lodestar Licensing Group LLC, Evanston, IL (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Nov. 21, 2023, as Appl. No. 18/515,692.
Application 18/515,692 is a continuation of application No. 17/690,223, filed on Mar. 9, 2022, granted, now 11,862,242.
Application 17/690,223 is a continuation of application No. 16/902,685, filed on Jun. 16, 2020, granted, now 11,276,463, issued on Mar. 15, 2022.
Prior Publication US 2024/0153556 A1, May 9, 2024
Int. Cl. G11C 11/00 (2006.01); G06F 16/2458 (2019.01); G11C 13/00 (2006.01); G06N 3/04 (2023.01)
CPC G11C 13/004 (2013.01) [G06F 16/2468 (2019.01); G11C 13/0026 (2013.01); G06N 3/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
an array of memory cells connected to a plurality of word lines and a plurality of bit lines;
an array of sense amplifiers coupled to the plurality of bit lines;
an array of drivers coupled to the plurality of word lines; and
a logic circuit configured to cause the drivers to apply an input pattern of voltages on the plurality of word lines according to a first pattern and configured to use the sense amplifiers to identify a bit line, among the plurality of bit lines.