US 12,283,316 B2
Cross-point pillar architecture for memory arrays
Innocenzo Tortorelli, Cernusco Sul Naviglio (IT); Fabio Pellizzer, Boise, ID (US); Mattia Robustelli, Milan (IT); and Alessandro Sebastiani, Piacenza (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 11, 2024, as Appl. No. 18/409,992.
Application 18/409,992 is a continuation of application No. 17/647,578, filed on Jan. 10, 2022, granted, now 11,887,661.
Claims priority of provisional application 63/266,155, filed on Dec. 29, 2021.
Prior Publication US 2024/0221829 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/003 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0023 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2213/71 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
applying a first selection voltage to a first access line and a second selection voltage to a second access line, wherein the first access line is coupled with a first end of a pillar, wherein the second access line is coupled with a second end of the pillar and a current mirror, and wherein the pillar is activated based at least in part on the first selection voltage and the second selection voltage;
deactivating the current mirror based at least in part on activating the pillar, wherein deactivating the current mirror is associated with a decrease in a magnitude of a voltage on the second access line; and
applying, after deactivating the current mirror, a programming voltage to a word line coupled with a memory material element, the memory material element coupled with the word line and the pillar, wherein a current through the memory material element flows from the first access line to the word line via a portion of the activated pillar based at least in part on applying the programming voltage to the word line and the decrease in the magnitude of the voltage of the second access line.