| CPC G11C 13/0026 (2013.01) [G11C 13/0028 (2013.01); G11C 13/0038 (2013.01)] | 13 Claims |
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1. A semiconductor device, comprising:
a memory cell array that includes:
a first plurality of first selection lines that extends in a first direction;
a second plurality of second selection lines that extends in a second direction; and
a plurality of memory cells, wherein each of the plurality of memory cells is between the first plurality of first selection lines and the second plurality of second selection lines;
a voltage generator configured to generate a selection voltage; and
a decoder section that includes a plurality of selection transistors and a gate driving section, wherein
the gate driving section includes a plurality of transistors,
the gate driving section is configured to:
select a first selection line of the first plurality of first selection lines;
apply the selection voltage to the selected first selection line;
drive each of a plurality of gates associated with each of the plurality of transistors; and
selectively apply a first driving voltage, a second driving voltage, and a third driving voltage to each of the plurality of gates,
each of the plurality of selection transistors is in a plurality of selection paths,
the first driving voltage is positive voltage,
the first driving voltage exceeds a withstand voltage,
the withstand voltage is associated with the plurality of selection transistors,
the second driving voltage corresponds to a negative voltage, and
a value of the third driving voltage ranges between a value of the first driving voltage and a value of the second driving voltage.
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