CPC G11C 11/419 (2013.01) [G11C 5/14 (2013.01); G11C 7/1048 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01)] | 4 Claims |
1. A static random-access memory comprising:
at least one six-transistor memory cell arranged between a first bitline, a second bitline and a word line;
a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the at least one six-transistor memory cell receiving a word line signal;
a main amplifier for receiving signals on data lines din and/din in a first voltage domain via a gate WEi; and
a main amplifier precharge circuit for precharging the main amplifier in response to a signal/PEMA such that the main amplifier amplifies signals in the first voltage domain to a second voltage domain, wherein the main amplifier functions as a write amplifier for amplifying a lower voltage on din to higher write voltage for writing to the at least one six-transistor memory cell.
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