US 12,283,313 B2
Low-power static random access memory
Katsuyuki Sato, Tokyo (JP); and William Martin Snelgrove, Toronto (CA)
Assigned to UNTETHER AI CORPORATION, Toronto (CA)
Filed by UNTETHER AI CORPORATION, Toronto (CA)
Filed on Aug. 21, 2023, as Appl. No. 18/235,935.
Application 18/235,935 is a continuation of application No. 18/251,251, granted, now 11,990,181, previously published as PCT/IB2022/055759, filed on Jun. 21, 2022.
Claims priority of provisional application 63/213,393, filed on Jun. 22, 2021.
Prior Publication US 2023/0395141 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 5/14 (2013.01); G11C 7/1048 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A static random-access memory comprising:
at least one six-transistor memory cell arranged between a first bitline, a second bitline and a word line;
a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the at least one six-transistor memory cell receiving a word line signal;
a main amplifier for receiving signals on data lines din and/din in a first voltage domain via a gate WEi; and
a main amplifier precharge circuit for precharging the main amplifier in response to a signal/PEMA such that the main amplifier amplifies signals in the first voltage domain to a second voltage domain, wherein the main amplifier functions as a write amplifier for amplifying a lower voltage on din to higher write voltage for writing to the at least one six-transistor memory cell.