US 12,283,312 B2
Short circuit detection in a read/write assist capacitor of a memory
Noam Jungmann, Holon (IL); Elazar Kachir, Tel Aviv (IL); Bishan He, Poughkeepsie, NY (US); Rajiv Joshi, Yorktown Heights, NY (US); Dureseti Chidambarrao, Weston, CT (US); Baozhen Li, South Burlington, VT (US); Atsushi Ogino, Fishkill, NY (US); and Klimentiy Shimanovich, Ramat Gan (IL)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 18, 2023, as Appl. No. 18/302,117.
Prior Publication US 2024/0355382 A1, Oct. 24, 2024
Int. Cl. G11C 11/417 (2006.01)
CPC G11C 11/417 (2013.01) 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a semiconductor substrate;
integrated circuitry on the semiconductor substrate, wherein the integrated circuitry includes:
a static random access memory (SRAM) cell array including a conductive line;
an assist circuit including a boost capacitor coupled to boost a voltage on the conductive line, wherein the boost capacitor includes first and second plates;
a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output; and
a sample circuit coupled to the output of the sense circuit, wherein the sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.