US 12,283,311 B2
Memory device and method for forming the same
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Feb. 10, 2023, as Appl. No. 18/167,617.
Claims priority of provisional application 63/377,348, filed on Sep. 28, 2022.
Prior Publication US 2024/0105258 A1, Mar. 28, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 7/00 (2006.01); G11C 11/412 (2006.01); H01L 23/48 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/412 (2013.01) [G11C 7/00 (2013.01); H01L 23/481 (2013.01); H10B 10/125 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a memory device, comprising:
forming a first pull-up transistor, a first pull-down transistor, a first pass-gate transistor, a second pull-up transistor, a second pull-down transistor, a second pass-gate transistor over a substrate;
forming a first bit line electrically connected to a source/drain epitaxy structure of the first pass-gate transistor;
forming a second bit line electrically connected to a source/drain epitaxy structure of the second pass-gate transistor;
forming a word line electrically connected to gate structures of the first pass-gate transistor and the second pass-gate transistor;
removing the substrate to expose a bottom surface of a source/drain epitaxy structure of the first pull-down transistor and a bottom surface of a source/drain epitaxy structure of the second pull-down transistor; and
forming a first power line electrically connected to the bottom surface of the source/drain epitaxy structure of the first pull-down transistor and electrically connected to the bottom surface of the source/drain epitaxy structure of the second pull-down transistor.