| CPC G11C 11/4097 (2013.01) [H10B 12/20 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02)] | 10 Claims |
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1. A semiconductor memory device comprising:
a first insulating layer disposed on a substrate, wherein a direction in parallel to an upper surface of the substrate is defined an X direction, a direction in perpendicular to the upper surface of the substrate is defined a Z direction, and a direction in perpendicular to both the X and Z directions is defined a Y direction;
a plurality of first impurity layers placed separately from the first insulating layer and each extending in the X direction, wherein the plurality of first impurity layers are placed one over another in the Z direction and each have first and second ends;
a plurality of semiconductor layers each having first and second ends, wherein the plurality of semiconductor layers each extend in the X direction from the second end of a corresponding first impurity layer with the first end of the semiconductor layer being in contact with the second end of the corresponding first impurity layer;
a plurality of second impurity layers each having first and second ends, wherein the plurality of second impurity layers each extend in the X direction from the second end end of a corresponding semiconductor layer with the first end of the second impurity layer being in contact with the second end of the corresponding semiconductor layer;
a plurality of gate insulating layers covering the plurality of semiconductor layers, respectively, wherein the plurality of gate insulating layers partially cover the plurality of first impurity layers and the plurality of second impurity layer, respectively;
a first gate conductor layer disposed in contact with the plurality of gate insulating layers in proximity to the plurality of first impurity layers;
a plurality of second gate conductor layers disposed, separately from the first gate conductor layer, in contact with the plurality of gate insulating layers in proximity to the plurality of second impurity layers;
a first conductor layer connected to the first ends of the plurality of first impurity layers;
a second conductor layer connected to the second ends of the plurality of second impurity layers;
a second insulating layer contacting the first insulating layer, the first gate conductor layer, and the first conductor layer; and
a third insulating layer contacting the first insulating layer, the plurality of second gate conductor layers, and the second conductor layer, wherein
memory write operation is performed by controlling voltage applied to each of the first conductor layer, the second conductor layer, the first gate conductor layer, and the plurality of second gate conductor layers to perform operation of generating electrons and holes in the plurality of semiconductor layers through an impact ionization phenomenon with current flowing between the plurality of first impurity layers and the plurality of second impurity layers or through gate induced drain leakage current and perform operation of retaining, in the plurality of semiconductor layers, some or all of the generated electrons or holes that are majority carriers in the plurality of semiconductor layers,
memory erase operation is performed by controlling voltage applied to each of the first conductor layer, the second conductor layer, the first gate conductor layer, and the plurality of second gate conductor layers to remove the retained electrons or holes that are majority carriers in the semiconductor layers from at least either of the plurality of first impurity layers and the plurality of second impurity layers, and
the first conductor layer connected to the plurality of first impurity layers is connected to a source line, the second conductor layer connected to the plurality of second impurity layers is connected to a bit line, the first gate conductor layer is connected to a plate line, the plurality of second gate conductor layers are each connected to a word line, and predetermined voltage is provided to each of the source line, the bit line, the plate line, and the word line to perform memory writing and erasure.
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