US 12,283,309 B2
Pseudo-static random-access memory and reading method thereof
Junichi Sasaki, Kanagawa (JP); and Kaoru Mori, Kanagawa (JP)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Apr. 25, 2023, as Appl. No. 18/306,249.
Claims priority of application No. 2022-073917 (JP), filed on Apr. 28, 2022.
Prior Publication US 2023/0352083 A1, Nov. 2, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/40615 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A pseudo-static random-access memory, comprising:
a memory array;
an input/output circuit configured to receive a read command sequence from a data input/output pin, and generate a read command, a read row address, and a read column address according to the read command sequence;
a count-and-command decoder coupled to the input/output circuit and configured to:
receive an internal enable signal, a clock signal, and the read command,
decode the read command,
start counting the clock signal when the internal enable signal changes from a disable state to an enable state, and
output a column address strobe signal at a first level when a count of the clock signal reaches a first clock amount;
a burst-length counter coupled to the count-and-command decoder and configured to:
receive the clock signal, the internal enable signal, and the column address strobe signal, and
count the clock signal during a period starting from when the column address strobe signal changes from a second level to the first level to when the internal enable signal changes from an enable state to a disable state, so as to provide a burst length accordingly;
a row-and-column control circuit coupled to the input-output circuit and the count-and-command decoder and configured to:
receive the clock signal, a column select enable signal, and the read column address, and
in response to the clock signal, output a column select signal to the memory array according to the read column address when the column select enable signal changes from the second level to the first level; and
a delay control circuit coupled to the row-and-column control circuit and the burst-length counter and configured to:
receive the column select enable signal and the burst length, and
output a first confirmation signal at the first level to the row-and-column control circuit after the column select enable signal changes from the second level to the first level and is then delayed by the burst length, such that a length of the column select signal is equal to the burst length.