US 12,283,308 B2
Memory device and method for operating the same
Kuang Ting Chen, Taipei (TW); Peijiun Lin, Kaohsiung (TW); Ching-Wei Wu, Nantou County (TW); and Feng-Ming Chang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 10, 2023, as Appl. No. 18/152,635.
Claims priority of provisional application 63/403,952, filed on Sep. 6, 2022.
Prior Publication US 2024/0079050 A1, Mar. 7, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an array of bit cells; and
a set of tracking cells arranged adjacent to the array of bit cells along a first direction, and comprising:
a set of first tracking cells coupled to a first tracking bit line for transmitting a first tracking signal corresponding to a read tracking operation; and
a set of second tracking cells coupled to a second tracking bit line, separated from the first tracking bit line, for transmitting a second tracking signal corresponding to a write tracking operation,
wherein the set of second tracking cells are arranged adjacent to the set of first tracking cells along a second direction that is different from the first direction;
wherein first tracking cells in the set of first tracking cells are coupled in series with each other and arranged along the second direction, and second tracking cells in the set of second tracking cells are coupled in series with each other and arranged along the second direction.