US 12,283,307 B2
Memory control circuit providing die-level read retry table, memory package, and storage device
Jae Yong Son, Icheon-si (KR); Nam Kyeong Kim, Icheon-si (KR); Hoon Cho, Icheon-si (KR); Hyuk Min Kwon, Icheon-si (KR); Dae Sung Kim, Icheon-si (KR); Jang Seob Kim, Icheon-si (KR); and Sang Ho Yun, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 7, 2022, as Appl. No. 18/063,007.
Claims priority of application No. 10-2022-0091896 (KR), filed on Jul. 25, 2022.
Prior Publication US 2024/0029787 A1, Jan. 25, 2024
Int. Cl. G11C 11/56 (2006.01); G11C 11/4078 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4078 (2013.01); G11C 11/4085 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A storage device comprising:
a memory including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, and including a special block that stores a read retry table in which a plurality of read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions; and
a controller configured to control the memory and perform a read retry operation for the memory using the read retry table,
wherein the read retry table is optimized for each condition with respect to the memory by obtaining samples of read voltages for each of the plurality of first conditions and each of the plurality of second conditions and clustering the samples through machine learning.