| CPC G11C 11/409 (2013.01) [H10B 12/20 (2023.02)] | 11 Claims |
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1. A memory device including a semiconductor element, the memory device comprising a memory cell, wherein
the memory cell includes:
a semiconductor base material extending in a direction horizontal to a substrate;
a first impurity region formed in a direction in which the semiconductor base material extends;
a first gate insulating layer partially covering the semiconductor base material and the first impurity region;
a first gate conductor layer formed in proximity to the first impurity region and partially covering the first gate insulating layer;
a second gate insulating layer partially covering the first semiconductor base material without contacting the first gate conductor layer;
a second gate conductor layer partially covering the second gate insulating layer without contacting the first gate conductor layer; and
a second impurity region formed at part of the semiconductor base material between the first gate conductor layer and the second gate conductor layer,
the first impurity region is connected to a bit line, the second impurity region is connected to a source line, the first gate conductor layer is connected to a word line, the second gate conductor layer is connected a plate line, and
memory writing and/or erasure is performed by applying independent voltage to each of the source line, the bit line, the plate line, and the word line.
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