US 12,283,305 B2
Main word line drivers
John Schreck, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jan. 12, 2022, as Appl. No. 17/573,854.
Prior Publication US 2023/0223069 A1, Jul. 13, 2023
Int. Cl. G11C 11/40 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4085 (2013.01) [G11C 11/4087 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a main word line;
a first transistor coupled between a first potential and the main word line, wherein the first transistor is configured to be in an on state when a first address signal provided to a gate of the first transistor is in a first state and configured to be in an off state when the first address signal is in a second state;
a second transistor coupled between the first potential and the main word line, wherein the second transistor is configured to be in a high resistance state; and
a third transistor coupled between a second potential and the main word line, wherein the third transistor is configured to be in an on state when the first address signal provided to a gate of the third transistor is in the second state and configured to be in an off state when the address signal is in the first state,
wherein the main word line is driven to the first potential when the first transistor is in the on state.