| CPC G11C 11/40622 (2013.01) [G11C 11/40615 (2013.01); G11C 11/4085 (2013.01)] | 18 Claims |

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1. A memory device comprising:
a volatile memory cell array coupled to a plurality of word lines;
a refresh operation circuit configured to perform, in response to one of a refresh command and an eviction control signal, a corresponding one of a refresh operation and an eviction operation on a word line selected by a refresh address among the word lines; and
a table management circuit configured to:
count, as respective counting numbers for each of a plurality of row addresses, a number of times that each of the row addresses corresponding to the word lines is used for the refresh operation,
select, as a selected row addresses, one or more among the row addresses on the basis of the respective counting numbers corresponding to the plurality of row addresses,
store the selected row addresses in a refresh table, and
control whether to enable the eviction control signal on the basis of a row address having a counting number exceeding a reference number among the selected row addresses stored in the refresh table.
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