| CPC G11C 11/40615 (2013.01) [G11C 11/40622 (2013.01); G11C 11/4085 (2013.01); G11C 11/4096 (2013.01)] | 8 Claims |

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1. An electronic device comprising:
a count signal generation circuit configured to increase one of values of a weak cell count signal and an active count signal by comparing a weak cell address with an adjacent address generated from a row address, when an active operation is performed; and
a target refresh control circuit configured to:
latch the adjacent address based on the values of the weak cell count signal and the active count signal, and
output the latched adjacent address as a target address for a refresh operation based on a target refresh signal,
wherein, the weak cell address is a location of a weak cell, which is a memory cell with relatively low data retention characteristics.
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