US 12,283,302 B2
Memory circuit, signal transmission system and signal transmission method
Shun-Ke Wu, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jan. 8, 2023, as Appl. No. 18/151,459.
Prior Publication US 2024/0233799 A1, Jul. 11, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/04 (2006.01); G11C 11/406 (2006.01)
CPC G11C 11/40607 (2013.01) [G11C 7/04 (2013.01); G11C 7/1051 (2013.01); G11C 7/106 (2013.01); G11C 7/1078 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory circuit, comprising:
a signal buffer, configured to receive a strobe signal;
a plurality of switch circuits, configured to be coupled to the signal buffer through a plurality of signal paths respectively, wherein the lengths of the plurality of signal paths are equal;
a temperature sensor, coupled to the plurality of switch circuits and configured to conduct one of the plurality of switch circuits according to the temperature of the memory circuit in response to receiving a sensing command;
a path-length-compensation circuit, comprising a plurality of input terminals connected in series, wherein the plurality of input terminals are configured to respectively receive the outputs of the plurality of switch circuits; and
at least one data latch, coupled to an output terminal of the path-length-compensation circuit and configured to store or output data according to the output of the path-length-compensation circuit,
wherein in response to the temperature of the memory circuit exceeding a first temperature threshold, the temperature sensor conducts a first switch circuit of the plurality of switch circuits,
wherein in response to the temperature of the memory circuit exceeding a second temperature threshold, the temperature sensor conducts a second switch circuit of the plurality of switch circuits, wherein the first temperature threshold is higher than the second temperature threshold, and
wherein the first switch circuit and the second switch circuit are respectively coupled to a first input terminal and a second input terminal of the plurality of input terminals, and the first input terminal is coupled between the at least one data latch and the second input terminal.