US 12,283,301 B2
Semiconductor memory device and operating method thereof
Chul Moon Jung, Gyeonggi-do (KR); and Woongrae Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on May 25, 2022, as Appl. No. 17/824,634.
Claims priority of application No. 10-2022-0000256 (KR), filed on Jan. 3, 2022.
Prior Publication US 2023/0215484 A1, Jul. 6, 2023
Int. Cl. G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/406 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory cell region including a plurality of cell mats in each of which a plurality of rows are disposed, each row coupled to normal cells and row-hammer cells;
a repair control circuit configured to generate a pairing flag denoting whether a cell mat in which an active row corresponding to an active address is disposed, is repaired with another cell mat; and
a refresh control circuit configured to:
select, when an active command is inputted, a sampling address based on first and second data read from the row-hammer cells of the active row,
refresh, when a target refresh command is inputted, one or more adjacent rows to a target row corresponding to the sampling address while selectively refreshing one or more adjacent rows to a paired row of the target row according to the pairing flag,
wherein the paired row of the target row is both disposed in another cell mat which stores repair data for a cell mat including the target row and activated together with the target row.