US 12,283,300 B2
Devices, methods, and systems for a multilevel memory cell
Stefano Sivero, Comun Nuovo (IT)
Assigned to FERROELECTRIC MEMORY GMBH, Dresden (DE)
Filed by Ferroelectric Memory GmbH, Dresden (DE)
Filed on Dec. 2, 2022, as Appl. No. 18/074,101.
Prior Publication US 2024/0185903 A1, Jun. 6, 2024
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/221 (2013.01) [G11C 11/2273 (2013.01); G11C 11/2275 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory comprising:
a memory element that is writable to at least three different remanent polarization states;
a sensing circuit configured to determine, in a read operation, a stored state of the memory element from among the at least three different remanent polarization states based on a sensed change in a remanent polarization of the memory element caused by an applied read voltage configured to cause a voltage drop across the memory element sufficient to write the memory element to one of the at least three different remanent polarization states;
a biasing circuit configure to, in a write operation, apply a bias voltage level across the memory element to write the memory element to the stored state.