US 12,283,297 B2
Memory device
Kuniaki Sugiura, Seoul (KR); and Taichi Igarashi, Seoul (KR)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 17, 2022, as Appl. No. 17/843,084.
Claims priority of application No. 2022-044000 (JP), filed on Mar. 18, 2022.
Prior Publication US 2023/0298647 A1, Sep. 21, 2023
Int. Cl. G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC G11C 11/161 (2013.01) [G11C 11/1675 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first memory cell;
a second memory cell;
a first circuit configured to supply a write current to the first memory cell and the second memory cell;
a first wiring coupled to the first circuit;
a first electrode configured to electrically couple the first memory cell to the first wiring; and
a second electrode configured to electrically couple the second memory cell to the first wiring,
wherein:
a length of the first wiring from the first circuit to the first electrode is smaller than a length of the first wiring from the first circuit to the second electrode, and
a resistance value of the first electrode is higher than a resistance value of the second electrode.