| CPC G09G 3/3275 (2013.01) [G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/0252 (2013.01); G09G 2330/021 (2013.01); G09G 2350/00 (2013.01)] | 17 Claims |
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1. A display driver integrated circuit (IC) comprising:
a clock generator configured to generate an internal operating clock; and
a control circuit configured to provide a data signal to a pixel array based on the internal operating clock, wherein the data signal corresponds to frame data,
wherein the control circuit is further configured to, in a frame data update period:
receive first frame data,
perform a first synchronization operation on the internal operating clock based on the first frame data, and
provide a first data signal to the pixel array for display of an image, and
wherein the control circuit is further configured to, in a low power mode (LPM) period when an update of the frame data is not performed:
transmit a sync request signal based on a result of monitoring a state of a display panel,
receive a frequency signal from a System-on-Chip (SoC) in response to the sync request signal, and
perform a second synchronization operation on the internal operating clock based on the frequency signal,
whereby the display driver IC is configured to determine a frequency difference has occurred between a panel clock and a processor clock during a first portion of the LPM period, and update a frequency of the panel clock to synchronize with the processor clock during a second portion of the LPM period, and thereby eliminate a flicker in the image at a time of a frame update, wherein the panel clock is the internal operating clock, the processor clock is the frequency signal from the SoC, and the sync request signal is sent based on the determination of the frequency difference.
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