| CPC G09G 3/3266 (2013.01) [G09G 3/32 (2013.01); H10K 59/1216 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/0291 (2013.01); G09G 2330/04 (2013.01)] | 30 Claims |
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1. A display device comprising:
a substrate including a display area in which one or more images are displayed and a non-display area different from the display area; and
a gate driving panel circuit configured to output a plurality of scan signals to a plurality of scan signal lines disposed in the display area,
wherein the gate driving panel circuit comprises:
an output buffer block comprising a scan output buffer configured to receive a clock signal and output a scan signal among the plurality of scan signals, and
a logic block configured to control respective voltages of a Q node and a QB node, which are electrically connected to the output buffer block,
wherein the scan output buffer comprises:
a scan pull-up transistor disposed between a clock node to which the clock signal is input and a scan output node from which the scan signal is output, and
a scan pull-down transistor disposed between a gate low voltage node to which a gate low voltage is applied and the scan output node,
wherein a gate node of the scan pull-up transistor is electrically connected to the Q node, and the scan output buffer comprises a first capacitor disposed between the gate node and a source node of the scan pull-up transistor, and
wherein the first capacitor comprises at least two sub-capacitor regions.
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