US 12,283,246 B2
Organic light emitting diode display substrate and preparation method thereof, and organic light emitting diode display apparatus
Jiangnan Lu, Beijing (CN); Guangliang Shang, Beijing (CN); Libin Liu, Beijing (CN); Li Wang, Beijing (CN); Xinshe Yin, Beijing (CN); and Shiming Shi, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/636,898
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Mar. 24, 2021, PCT No. PCT/CN2021/082655
§ 371(c)(1), (2) Date Feb. 21, 2022,
PCT Pub. No. WO2022/198487, PCT Pub. Date Sep. 29, 2022.
Prior Publication US 2023/0351970 A1, Nov. 2, 2023
Int. Cl. G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01); G11C 19/28 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a display region and a non-display region, wherein the non-display region is provided with a gate drive circuit comprising a plurality of cascaded shift register units; each shift register unit comprises an input sub-circuit and a denoising output sub-circuit; the denoising output sub-circuit is connected with the input sub-circuit, a first group of clock signal lines, and a second group of clock signal lines, and the input sub-circuit is connected with a third group of clock signal lines;
the third group of clock signal lines, the input sub-circuit, the first group of clock signal lines, the denoising output sub-circuit, and the second group of clock signal lines are sequentially arranged along a first direction;
the denoising output sub-circuit comprises: a denoising control unit; the first group of clock signal lines comprises a first clock signal line and a second clock signal line;
the denoising control unit at least comprises a first transistor, a second transistor, a first capacitor, and a second capacitor; a control electrode and a first electrode of the first transistor are connected with a second denoising control node, and a second electrode of the first transistor is connected with a first denoising control node; a control electrode of the second transistor is connected with the first clock signal line, a first electrode of the second transistor is connected with a first power supply line, and a second electrode of the second transistor is connected with the second denoising control node; a first electrode of the first capacitor is connected with the second denoising control node, a second electrode of the first capacitor is connected with the second clock signal line; a first electrode of the second capacitor is connected with the first denoising control node, and a second electrode of the second capacitor is connected with the first power supply line; and
the first capacitor is adjacent to the first transistor, and the second capacitor is adjacent to the first transistor.