US 12,283,241 B2
Pixel driving circuit, driving method thereof, and display panel
Xuanyun Wang, Hubei (CN); and Chao Dai, Hubei (CN)
Assigned to WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Wuhan (CN)
Filed by WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Hubei (CN)
Filed on Sep. 28, 2023, as Appl. No. 18/476,315.
Application 18/476,315 is a continuation in part of application No. 17/267,010, granted, now 11,804,177, previously published as PCT/CN2020/114218, filed on Sep. 9, 2020.
Claims priority of application No. 202010724888.9 (CN), filed on Jul. 24, 2020; and application No. 202010752675.7 (CN), filed on Jul. 30, 2020.
Prior Publication US 2024/0021159 A1, Jan. 18, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3258 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/043 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A display panel, comprising a pixel driving circuit, wherein the pixel driving circuit comprises:
a first power supply, a second power supply, a first transistor, a second transistor, a storage capacitor, and a light-emitting diode, wherein the first transistor, the second transistor, and the light-emitting device are connected in series between the first power supply and the second power supply;
a third transistor, wherein one of a source or a drain of the third transistor is electrically connected to a data signal line, the other one of the source or the drain of the third transistor is electrically connected to an electrode plate of the storage capacitor, and the other electrode plate of the storage capacitor is electrically connected to a gate of the first transistor; and
a fourth transistor, wherein one of a source or a drain of the fourth transistor is electrically connected to a first reset signal line, the other of the source or the drain of the fourth transistor is electrically connected to the other electrode plate of the storage capacitor,
a sixth transistor, wherein one of a source or a drain of the sixth transistor is electrically connected between a second reset signal line and the other of the source or drain of the first transistor, and a second reset signal is different from a first reset signal,
the first transistor accompanying with the sixth transistor and the storage capacitor is configured to compensate a threshold voltage of the first transistor.