| CPC G09G 3/32 (2013.01) [H04N 25/74 (2023.01); H04N 25/76 (2023.01); G09G 2310/0291 (2013.01)] | 17 Claims |

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1. A semiconductor device comprising:
a first buffer circuit and a second buffer circuit each configured to output a control signal to one control line based on an input from a signal output circuit; and
an element configured to receive the control signal transmitted through the one control line,
wherein the second buffer circuit is switchable between electrical connection and electrical disconnection to the one control line, and
wherein a first mode in which a current is supplied to the one control line with a first driving capability by the first buffer circuit, and a second mode in which a current is supplied to the one control line with a second driving capability greater than the first driving capability by connecting both the first buffer circuit and the second buffer circuit to the one control line, are switchable.
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