| CPC G09G 3/32 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/08 (2013.01)] | 20 Claims |

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1. A gate driver of a display device comprising:
an inverter configured to invert a start signal to generate an inverted start signal;
a first driver including a first stage configured to generate a bias gate signal to initialize a light emitting element of each of pixels in the display device in response to the inverted start signal; and
a second driver including a second stage configured to generate a write gate signal to apply data voltages to the pixels in the display device in response to the start signal,
wherein the first driver further receives a first clock signal and a second clock signal whose phase is different than the first clock signal to generate the bias gate signal.
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