| CPC G09G 3/2096 (2013.01) [G09G 2320/0247 (2013.01)] | 27 Claims |

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1. An electronic device comprising:
a host processor configured to generate a first clock signal and to output frame data and a synchronization signal, wherein the synchronization signal toggles based on the first clock signal;
a driving controller connected to the host processor, and configured to receive the synchronization signal and the frame data from the host processor and to generate a control signal based on a second clock signal; and
a display panel configured to be driven based on the control signal,
wherein the driving controller synchronizes the second clock signal with the first clock signal based on the synchronization signal,
wherein the driving controller includes an error detector configured to detect an error of the synchronization signal,
wherein the error is one of an initial synchronization fail error indicating that the driving controller did not receive the synchronization signal and a synchronization loss error indicating that a portion of the synchronization signal was omitted, and
wherein the error detector outputs a first signal when the error is the initial synchronization fail error and outputs a second signal different from the first signal when the error is the synchronization loss error.
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