US 12,283,218 B2
Driving circuit, display device, and driving method
Wenpeng Ma, Beijing (CN); Shulin Yao, Beijing (CN); Yanping Liao, Beijing (CN); Panhui Zhao, Beijing (CN); Dongchuan Chen, Beijing (CN); Pengfei Hu, Beijing (CN); Zheng Zhang, Beijing (CN); and Yingmeng Miao, Beijing (CN)
Assigned to Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/027,534
Filed by Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Mar. 30, 2022, PCT No. PCT/CN2022/084071
§ 371(c)(1), (2) Date Mar. 21, 2023,
PCT Pub. No. WO2023/184238, PCT Pub. Date Oct. 5, 2023.
Prior Publication US 2024/0296775 A1, Sep. 5, 2024
Int. Cl. G09G 5/00 (2006.01); G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 3/2007 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A driving circuit, comprising a level conversion unit and a gate electrode driving unit,
wherein the level conversion unit comprises a plurality of first clock signal input terminals and a plurality of first clock signal output terminals, and the level conversion unit is configured to convert a plurality of first clock signals received by the plurality of first clock signal input terminals into a plurality of second clock signals and provide a plurality of first output signals to the gate electrode driving unit by the plurality of first clock signal output terminals, respectively;
the gate electrode driving unit comprises a plurality of second clock signal input terminals and 2n gate signal output terminals, the plurality of second clock signal input terminals are configured to receive the plurality of first output signals, and n is an integer greater than or equal to 2; the gate electrode driving unit comprises a plurality of cascaded shift register units, each of the 2n gate signal output terminals is configured to provide a gate scanning signal for one pixel row in a pixel array of a display panel;
the gate electrode driving unit is configured to sequentially shift and output a plurality of first gate scan signals by a first portion of the 2n gate signal output terminals of a first portion of the plurality of cascaded shift register units in response to a first portion of the plurality of first output signals received at a first moment by a first portion of the plurality of second clock signal input terminals, and sequentially output a plurality of second gate scan signals by a second portion of the 2n gate signal output terminals of a second portion of the plurality of cascaded shift register units in response to a second portion of the plurality of first output signals received at a second moment by a second portion of the plurality of second clock signal input terminals; and
at the first moment, the first gate scan signals are trigger signals to enable the pixel rows receiving the first gate scan signals to be in an on state, and the second gate scan signals are non-trigger signals to enable the pixel rows receiving the second gate scan signals to be in an off state; at the second moment, the first gate scan signals are non-trigger signals to enable the pixel rows receiving the first gate scan signals to be in an off state, and the second gate scan signals are trigger signals to enable the pixel rows receiving the second gate scan signals to be in an on state.