US 12,282,800 B2
Thread replay to preserve state in a barrel processor
Chris Baronne, Allen, TX (US); Dean E. Walker, Allen, TX (US); and John Amelio, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 20, 2020, as Appl. No. 17/075,013.
Prior Publication US 2022/0121485 A1, Apr. 21, 2022
Int. Cl. G06F 9/48 (2006.01); G06F 1/10 (2006.01); G06F 9/46 (2006.01); G06F 9/50 (2006.01); G06F 12/0875 (2016.01)
CPC G06F 9/4881 (2013.01) [G06F 1/10 (2013.01); G06F 9/46 (2013.01); G06F 9/466 (2013.01); G06F 9/48 (2013.01); G06F 9/4843 (2013.01); G06F 9/485 (2013.01); G06F 9/50 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a barrel processor, comprising:
a temporary memory; and
a thread scheduling circuitry;
wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to:
schedule a current thread to place into a pipeline for the barrel processor on a clock cycle, the barrel processor to schedule threads on each clock cycle;
store the current thread in the temporary memory while the current thread is being executed in the pipeline;
detect that no thread is available to schedule from a thread scheduling queue on a clock cycle subsequent to the clock cycle that the current thread is scheduled; and
in response to detecting that no thread is available on the subsequent clock cycle, repeat scheduling the current thread based on contents of the temporary memory instead of the thread scheduling queue.