US 12,282,779 B2
Instruction retirement unit, instruction execution unit, processing unit, computing device, and instruction processing method for performing retirement processing on instructions based on instruction completion information
Chang Liu, Pudong New Area (CN); Haowen Chen, Hangzhou (CN); and Tao Jiang, Hangzhou (CN)
Assigned to C-SKY MICROSYSTEMS CO., LTD., Hangzhou (CN)
Filed by C-SKY MICROSYSTEMS CO., LTD., Hangzhou (CN)
Filed on Dec. 30, 2022, as Appl. No. 18/148,759.
Claims priority of application No. 202210667352.7 (CN), filed on Jun. 14, 2022.
Prior Publication US 2023/0401062 A1, Dec. 14, 2023
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3854 (2023.08) [G06F 9/3856 (2023.08); G06F 9/3858 (2023.08); G06F 9/3861 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
at least one processor; and
a memory communicatively connected with the at least one processor, wherein
the memory stores processor instructions executable by the at least one processor, and the processor instructions, when executed by the at least one processor, cause an instruction retirement unit, of the at least one processor, to:
receive a completion request signal, which is sent by an instruction execution unit for instructions to be completed, wherein the completion request signal is used to request completion of the instructions to be completed;
after determining, based on a new-old relationship between retired instructions and the instructions to be completed, that the instructions to be completed can be completed, send, to the instruction execution unit, a completion permission signal for the instructions to be completed, receive instruction completion information of the instructions to be completed sent from the instruction execution unit, and store the instruction completion information of the instructions to be completed into instruction buffer table entries in a buffer, wherein a number of the instruction buffer table entries in the buffer is greater than 1 and less than an out-of-order degree allowed by the at least one processor, each of the instruction buffer table entries is used to store the instruction completion information of one instruction; and
perform, based on the instruction completion information stored in each of the instruction buffer table entries, retirement processing on instructions that have already been completed and have not been retired, and delete the instruction completion information of the retired instructions from the instruction buffer table entries.