| CPC G06F 9/30036 (2013.01) [G06F 9/30145 (2013.01); G06F 9/321 (2013.01); G06F 9/3816 (2013.01); G06F 9/3836 (2013.01); G06F 9/3838 (2013.01); G06F 9/3856 (2023.08); G06F 9/3877 (2013.01)] | 16 Claims |
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1. A coprocessor that is coupled to a processor that executes instructions, the coprocessor processing coprocessor instructions, including a first committed coprocessor index load instruction, received from the processor, the coprocessor comprising:
a vector data buffer comprising a plurality of data banks which are coupled to vector data registers to route data from any of the plurality of data banks to an element of a selected vector data register or to route data from an element of the selected vector data register to any data bank of the vector data buffer;
a coprocessor issue circuit for receiving the first committed coprocessor index load instruction, and issuing the first committed coprocessor index load instruction;
a coprocessor execution queue coupled to the coprocessor issue circuit to receive the first committed coprocessor index load instruction from the coprocessor issue circuit and dispatch the first committed coprocessor index load instruction to the vector data buffer to read data for a plurality of elements of the vector data register;
a coprocessor time counter that increments a coprocessor time count with each clock cycle as provided by a clock circuit of the processor, the coprocessor time counter comprising a coprocessor N-bit counter wherein an Nth-bit count value represents a largest future time for the coprocessor issue circuit to dispatch a coprocessor instruction, wherein the coprocessor N-bit counter returns to a zero count after reaching the Nth-bit count value;
wherein each instruction executed by the coprocessor is executed at a preset execution time correlated to the coprocessor time count;
wherein the coprocessor issue circuit issues a first committed coprocessor instruction with a preset coprocessor execution time based on the coprocessor time count;
wherein the coprocessor execution queue dispatches the first committed coprocessor instruction to a coprocessor functional circuit based upon the coprocessor the time count;
wherein the coprocessor time counter is frozen when result data are not valid at the preset execution time or read data from a vector register file are not accepted by a first coprocessor functional circuit;
wherein the coprocessor time counter is unfrozen when the result data are valid or the read data are accepted by the first coprocessor functional circuit; and
wherein the coprocessor first coprocessor functional circuit further comprises,
a latency counter which is set to equal a latency time of a first coprocessor instruction when the first coprocessor instruction is received by the first coprocessor functional circuit, the latency counter causing result data to be written back to a vector register of the vector register file upon counting down to zero; and
an alternative time counter that continues incrementing when the coprocessor time counter is frozen and the latency counter is not zero, wherein an alternative time count generated by the alternative time counter is used for writing back data to the register file from the first coprocessor functional circuit.
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