US 12,282,721 B2
Netlist design for post silicon local clock controller timing improvement
Michael Kazda, Poughkeepsie, NY (US); Sean Michael Carey, Dutchess, NY (US); Frank J. Musante, Poughkeepsie, NY (US); and Michael Hemsley Wood, Wilmington, DE (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Mar. 2, 2022, as Appl. No. 17/684,451.
Prior Publication US 2023/0281365 A1, Sep. 7, 2023
Int. Cl. G06F 30/327 (2020.01)
CPC G06F 30/327 (2020.01) 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
determining, by a processor, a netlist for an integrated circuit design, wherein the netlist comprises a design for placement of a plurality of latches within an integrated circuit;
determining a set of timing paths from the netlist, wherein each timing path in the set of timing paths comprises a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit;
calculating a slack value for each timing path in the set of timing paths;
determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value;
calculating a score for each candidate timing path of the one or more candidate timing paths based on a count of a number of launch latch and capture latch pairs within the candidate timing path;
adjusting an interconnect for a first candidate timing path from the one or more candidate timing paths based on the first candidate timing path having a highest score of all scores for the one or more candidate timing path; and
generating an updated netlist based on the adjusting the interconnect for the first candidate timing path.