US 12,282,684 B2
Techniques for controlling command order
Christian M. Gyllenskog, Meridian, ID (US); and Luca Porzio, Casalnuovo (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 11, 2022, as Appl. No. 17/654,536.
Prior Publication US 2023/0289094 A1, Sep. 14, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0679 (2013.01); G06F 2212/7209 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more controllers associated with the memory system, wherein the one or more controllers are configured to cause the memory system to:
receive a plurality of commands each comprising a respective identifier corresponding to an order in which each command of the plurality of commands was generated;
determine a power on condition of the memory system;
determine, based at least in part on the power on condition, the plurality of commands performed prior to the power on, each command of the plurality of commands associated with one or more logical addresses and the respective identifier;
determine a discontinuity between the respective identifiers of a first subset of the plurality of commands and a second subset of the plurality of commands, wherein the identifiers of the first subset are continuous; and
invalidate the one or more logical addresses associated with commands of the second subset based at least in part on determining the discontinuity.