US 12,282,682 B2
Redundant computing across planes
Sean S. Eilert, Penryn, CA (US); Kenneth M. Curewitz, Cameron Park, CA (US); Helena Caminal, Ithaca, NY (US); and Ameen D. Akel, Rancho Cordova, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 17, 2024, as Appl. No. 18/415,285.
Application 18/415,285 is a continuation of application No. 17/652,229, filed on Feb. 23, 2022, granted, now 11,899,961.
Claims priority of provisional application 63/266,216, filed on Dec. 30, 2021.
Prior Publication US 2024/0152292 A1, May 9, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory die comprising a first memory plane and a second memory plane each comprising content-addressable memory cells; and
logic coupled with the memory die and configured to:
perform, based at least in part on sensing first data representative of a first set of contiguous bits of a vector from first content-addressable memory cells in the first memory plane, a computational operation on the first data stored in the first memory plane, wherein the computational operation is based at least in part on a first value, that is assigned to the first memory plane, for a bit that represents an arithmetic output associated with a second set of contiguous bits of the vector; and
perform, based at least in part on sensing second data representative of the first set of contiguous bits of the vector from second content-addressable memory cells in the second memory plane, the computational operation on the second data stored in the second memory plane, wherein the computational operation is based at least in part on a second value, that is assigned to the second memory plane, for the bit that represents the arithmetic output associated with the second set of contiguous bits of the vector.