US 12,282,669 B2
Prioritized power budget arbitration for multiple concurrent memory access operations
Luca Nubile, Sulmona (IT); Walter Di Francesco, Avezzano (IT); Fumin Gu, San Jose, CA (US); Ali Mohammadzadeh, Mountain View, CA (US); Biagio Iorio, Avezzano (IT); and Liang Yu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 29, 2024, as Appl. No. 18/621,747.
Application 18/621,747 is a continuation of application No. 17/668,311, filed on Feb. 9, 2022, granted, now 11,977,748.
Claims priority of provisional application 63/243,887, filed on Sep. 14, 2021.
Prior Publication US 2024/0272812 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
allocating power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter;
starting a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads; and
while the timer is running:
incrementing the priority ring counter before each power management cycle; and
prioritizing allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.