US 12,282,658 B1
System and method for large memory transaction (LMT) stores
Aadeetya Shreedhar, Natick, MA (US); Jason D. Zebchuk, Edinburgh (GB); Wilson P. Snyder, II, Holliston, MA (US); Albert Ma, Belmont, MA (US); and Joseph Featherston, Boston, MA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Feb. 21, 2024, as Appl. No. 18/583,457.
Application 18/583,457 is a continuation of application No. 17/937,128, filed on Sep. 30, 2022, granted, now 11,960,727.
Claims priority of provisional application 63/394,060, filed on Aug. 1, 2022.
Int. Cl. G06F 3/06 (2006.01); G06F 12/1045 (2016.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/1045 (2013.01); G06F 2212/1024 (2013.01)] 35 Claims
OG exemplary drawing
 
1. A system comprising:
a processor accelerator configured to perform a large memory transaction (LMT) store of a data set in response to an instruction, the LMT store including storing data from the data set, atomically, based on a LMT line (LMTLINE), the LMTLINE wider than a data-processing width of a processor issuing the instruction,
the processor accelerator further configured to send, to the processor, a response to the instruction.