| CPC G06F 21/602 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/30178 (2013.01); G06F 9/321 (2013.01); G06F 9/45558 (2013.01); G06F 9/48 (2013.01); G06F 9/5016 (2013.01); G06F 12/0207 (2013.01); G06F 12/0646 (2013.01); G06F 12/0811 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1408 (2013.01); G06F 12/1458 (2013.01); G06F 12/1466 (2013.01); G06F 21/12 (2013.01); G06F 21/6227 (2013.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01); H04L 9/0637 (2013.01); H04L 9/0822 (2013.01); H04L 9/0861 (2013.01); H04L 9/0869 (2013.01); H04L 9/0894 (2013.01); H04L 9/14 (2013.01); G06F 2009/45587 (2013.01); G06F 2212/1052 (2013.01); H04L 2209/125 (2013.01)] | 24 Claims |

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1. A processor, comprising:
a core including:
a first register to store a first cryptographically encoded pointer to a memory location, wherein a first portion of the first cryptographically encoded pointer is to include an encrypted slice of a base address of the memory location; and
circuitry to execute a first instruction to access the memory location, the first instruction to cause decoding and decrypting operations to be performed on the first cryptographically encoded pointer, the decoding and decrypting operations to include:
generating a decrypted slice of the base address, the generating the decrypted slice of the base address to include using a cryptographic algorithm based, at least in part, on a first tweak that includes context information associated with a first operand of the first instruction; and
generating a plaintext linear address based, at least in part, on the decrypted slice of the base address and an offset in the first cryptographically encoded pointer.
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