US 12,282,525 B2
Systems, methods, and apparatuses for matrix operations
Raanan Sade, Kibutz Sarid (IL); Simon Rubanovich, Haifa (IL); Amit Gradstein, Binyamina (IL); Zeev Sperber, Zichron Yackov (IL); Alexander Heinecke, San Jose, CA (US); Robert Valentine, Kiryat Tivon (IL); Mark J. Charney, Lexington, MA (US); Bret Toll, Hillsboro, OR (US); Jesus Corbal, King City, OR (US); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); and Menachem Adelman, Modi'in (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 3, 2023, as Appl. No. 18/386,771.
Application 18/386,771 is a continuation of application No. 15/859,268, filed on Dec. 29, 2017, granted, now 11,816,483.
Prior Publication US 2024/0143325 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 17/16 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30101 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
decode circuitry configured to decode at least an instance of a single instruction having an opcode and memory location information, wherein the opcode is to indicate execution circuitry is to retrieve configuration information about how storage of the apparatus was configured as two-dimensional data structures to be used by execution circuitry configured to perform two-dimensional matrix operations and store the retrieved configuration information as description data at a memory location to be identified from the memory location information, wherein the description data is to include a palette identifier, and a value to indicate a row to be used to restart; and
execution circuitry, in response to the decoded instance of the single instruction, to be configured to execute the decoded instance of the single instruction according to the opcode.