| CPC G06F 15/80 (2013.01) [G06F 9/30036 (2013.01); G06F 9/3836 (2013.01); G06F 15/7871 (2013.01)] | 20 Claims |

|
1. A method of operating a placer and router for an iterative placement and routing of a sorted operation unit graph on a reconfigurable processor, comprising:
receiving an architectural specification of the reconfigurable processor;
receiving the sorted operation unit graph comprising an ordered sequence of nodes and edges that interconnect nodes in the ordered sequence of nodes;
repeating as long as the ordered sequence of nodes comprises at least one unassigned node:
in order of the ordered sequence of nodes, assigning a first unassigned node from the ordered sequence of nodes as a currently assigned node to a location on the reconfigurable processor;
determining a search space on the reconfigurable processor for routing edges-to-be-routed of the edges, wherein the edges-to-be-routed connect the currently assigned node with previously assigned nodes of the ordered sequence of nodes;
determining legal shortest path routes on the reconfigurable processor in the search space for the edges-to-be-routed;
in response to unsuccessfully determining the legal shortest path routes on the reconfigurable processor in the search space for the edges-to-be-routed:
expanding the search space, and
returning to determining the legal shortest path routes on the reconfigurable processor in the search space for the edges-to-be-routed;
in response to successfully determining the legal shortest path routes on the reconfigurable processor in the search space for the edges-to-be-routed:
assigning the edges-to-be-routed to interconnection resources on the legal shortest path routes.
|