US 12,282,447 B2
Execution unit sharing between processing cores in a cluster of a system-on-chip (SoC)
Hithesh Hassan Lepaksha, Hyderabad (IN); Sharath Kumar Nagilla, Hyderabad (IN); and Darshan Kumar Nandanwar, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 22, 2023, as Appl. No. 18/473,119.
Prior Publication US 2025/0103545 A1, Mar. 27, 2025
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 15/78 (2006.01); G06F 15/80 (2006.01)
CPC G06F 15/7825 (2013.01) [G06F 9/3836 (2013.01); G06F 9/3858 (2023.08); G06F 15/7807 (2013.01); G06F 15/8076 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of execution unit (EU) sharing between processor cores, the method comprising:
encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core;
issuing a request for an idle execution unit of an inactive processor core;
sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core; and
replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.