US 12,282,439 B2
Dynamic page state aware scheduling of read/write burst transactions
Guanhao Shen, Austin, TX (US); Ravindra N. Bhargava, Austin, TX (US); and Kedarnath Balakrishnan, Bangalore (IN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Nov. 20, 2020, as Appl. No. 17/100,254.
Application 17/100,254 is a continuation of application No. 15/850,751, filed on Dec. 21, 2017, granted, now 10,846,253, issued on Nov. 24, 2020.
Prior Publication US 2021/0073152 A1, Mar. 11, 2021
Int. Cl. G06F 13/30 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/30 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 13/1626 (2013.01); G06F 13/1642 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a plurality of queues comprising circuitry configured to store memory access requests; and
control circuitry configured to:
send one or more first memory access requests stored in a first queue of the plurality of queues; and
send memory access requests stored in a second queue of the plurality of queues subsequent to the one or more first memory access requests having been sent, responsive to:
a cost for sending second memory access requests stored in the first queue being greater than a threshold cost; and
a cost for sending the memory access requests in the second queue being less than the threshold cost.