US 12,282,433 B2
Cache bypass
Emanuele Confalonieri, Segrate (IT); Patrick Estep, Rowlett, TX (US); Stephen S. Pawlowski, Beaverton, OR (US); and Nicola Del Gatto, Cassina de' Pecchi (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 27, 2023, as Appl. No. 18/215,117.
Claims priority of provisional application 63/356,392, filed on Jun. 28, 2022.
Prior Publication US 2023/0418756 A1, Dec. 28, 2023
Int. Cl. G06F 12/0888 (2016.01); G06F 12/0804 (2016.01)
CPC G06F 12/0888 (2013.01) [G06F 12/0804 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device; and
a memory controller, coupled to the memory device, comprising a cache, and configured to cause performance of a cache look-up operation associated with the cache, wherein the cache includes a cache sequence controller configured to:
determine a quantity of a given type of result of cache look-up operations associated with the cache;
determine the quantity satisfies a bypass threshold; and
cause performance of a bypass memory operation, substantially contemporaneously with the performance of the cache look-up operation, that bypasses the cache and accesses the memory device;
wherein performance of the cache look-up operation results in a cache miss; and
wherein, responsive to a determination that the cache is a clean cache, the cache sequence controller is configured to cache-in any data associated with the performance of the bypass memory operation in the cache.