US 12,282,432 B2
Graph memory engine
Michael J Miller, Saratoga, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 16, 2021, as Appl. No. 17/378,647.
Application 17/378,647 is a continuation of application No. PCT/US2020/048853, filed on Aug. 31, 2020.
Claims priority of provisional application 62/894,454, filed on Aug. 30, 2019.
Prior Publication US 2022/0114103 A1, Apr. 14, 2022
Int. Cl. G06F 12/0875 (2016.01)
CPC G06F 12/0875 (2013.01) [G06F 2212/452 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A method of operating a computation engine, the method comprising:
storing instructions in a memory;
operating the memory as an associative memory, wherein the memory comprises a content addressable memory (CAM) and wherein the instructions are identified by nodes of a tree of a memory graph; and
performing the instructions by the computation engine:
executing a first instruction of the instructions that is identified by a first node;
based on the first node comprising a branch to multiple nodes and based on the memory graph identifying a second node of the multiple nodes as a next branch node, selecting the second node of the multiple nodes as the next branch node;
based on the first node comprising the branch to multiple nodes and the memory graph identifying a third node of the multiple nodes as the next branch node, selecting the third node of the multiple nodes as the next branch node; and
executing a second instruction of the instructions identified by the next branch node.