US 12,282,398 B2
PCIe device and computing system including the same
Yong Tae Jeon, Gyeonggi-do (KR); Dong Jin Seong, Gyeonggi-do (KR); and Jong Heon Jeong, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Sep. 27, 2022, as Appl. No. 17/953,881.
Claims priority of application No. 10-2022-0039076 (KR), filed on Mar. 29, 2022.
Prior Publication US 2023/0315591 A1, Oct. 5, 2023
Int. Cl. G06F 11/20 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/2007 (2013.01) [G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A Peripheral Component Interconnect express (PCIe) device communicating with an external device, the PCIe device comprising:
a plurality of ports together with other ports included in the external device forming a plurality of lanes; and
a link controller configured to set a link including the plurality of lanes to allocate:
a first lane number to a first lane formed by a first port of the plurality of ports and a second port of the other ports among the plurality of lanes, and
a second lane number, which is non-sequential to the first lane number, to a second lane adjacent to the first lane and formed by a third port adjacent to the first port of the plurality of ports and a fourth port adjacent to the second port of the other ports among the plurality of lanes.
 
12. A computing system comprising:
a link including a plurality of lanes;
a first Peripheral Component Interconnect express (PCIe) device including a plurality of downstream ports; and
a second PCIe device including a plurality of upstream ports which form, together with the plurality of downstream ports, the plurality of lanes, and configured to transmit/receive data to/from the first PCIe device through the link,
wherein the first PCIe device is configured to set the link to allocate:
a first lane number to a first lane formed by a first downstream port of the plurality of downstream ports and a first upstream port of the plurality of upstream ports among the plurality of lanes, and
a second lane number, which is non-sequential to the first lane number, to a second lane adjacent to the first lane and formed by a second downstream port adjacent to the first downstream port of the plurality of downstream ports and a second upstream port adjacent to the first upstream port of the plurality of upstream ports among the plurality of lanes.
 
16. A computing system comprising:
a link including a plurality of lanes;
a first Peripheral Component Interconnect express (PCIe) device including a plurality of downstream ports; and
a second PCIe device including a plurality of upstream ports which form, together with the plurality of downstream ports, the plurality of lanes, and configured to transmit/receive data to/from the first PCIe device through the link,
wherein the first PCIe device is configured to provide the second PCIe device with sequential lane numbers allocated to the plurality of lanes,
wherein the second PCIe device is further configured to provide the first PCIe device with non-sequential lane numbers allocated to the plurality of lanes, and
wherein the non-sequential lane numbers include:
a first lane number allocated to a first lane formed by a first downstream port of the plurality of downstream ports and a first upstream port of the plurality of upstream ports among the plurality of lanes, and
a second lane number, which is non-sequential to the first lane number, allocated to a second lane adjacent to the first lane and formed by a second downstream port adjacent to the first downstream port of the plurality of downstream ports and a second upstream port adjacent to the first upstream port of the plurality of upstream ports among the plurality of lanes.