US 12,282,392 B2
Interconnects between chiplets and related link initialization protocols
Santhosh Reddy Akavaram, Hyderabad (IN); Prakhar Srivastava, Lucknow (IN); Aditya Singh Patel, Jabalpur (IN); and Yogananda Rao Chillariga, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 5, 2023, as Appl. No. 18/461,287.
Prior Publication US 2025/0077355 A1, Mar. 6, 2025
Int. Cl. G06F 11/00 (2006.01); G06F 11/14 (2006.01)
CPC G06F 11/1438 (2013.01) [G06F 11/1443 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A method for controlling a Universal Chiplet Interconnect Express (UCIe) link using a Link Training and Status State Machine (LTSSM), comprising:
determining a cause of a reset event in the LTSSM; and
initializing a main-band of the UCIe link in a main-band initialization state (MBINIT) of the LTSSM with a plurality of redundant main-band lanes being excluded in response to the cause being other than a trainerror or a linkerror.