US 12,282,389 B2
Error correction decoder, storage device including error correction decoder, and operating method thereof
Dae Sung Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 31, 2023, as Appl. No. 18/498,047.
Claims priority of application No. 10-2023-0028577 (KR), filed on Mar. 3, 2023.
Prior Publication US 2024/0296093 A1, Sep. 5, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/1048 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A storage device comprising:
a memory device configured to store data; and
a memory controller configured to:
iterate error correction decoding on data read from the memory device,
determine whether to continue iterating based on a result obtained by comparing a first threshold number with a number of Unsatisfied Check Nodes (UCNs) included in a syndrome of first decoded data, which is a result of a first set number of iterations of the error correction decoding on the read data, and
determine whether to continue iterating based on a result obtained by comparing a second threshold number with a number of UCNs included in a syndrome of second decoded data, which is a result of a sum of the first set number and a second set number of iterations of the error correction decoding on the read data.