US 12,282,378 B2
Techniques for memory access in a reduced power state
Binata Bhattacharyya, Hillsboro, OR (US); and Paul S. Diefenbaugh, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 11, 2023, as Appl. No. 18/196,309.
Application 18/196,309 is a continuation of application No. 17/522,294, filed on Nov. 9, 2021, granted, now 11,698,673.
Application 17/522,294 is a continuation of application No. 16/536,408, filed on Aug. 9, 2019, granted, now 11,256,318, issued on Feb. 22, 2022.
Prior Publication US 2023/0400908 A1, Dec. 14, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); G06F 1/3206 (2019.01); G06F 1/3287 (2019.01); G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 12/06 (2006.01)
CPC G06F 1/3287 (2013.01) [G06F 1/3206 (2013.01); G06F 3/0625 (2013.01); G06F 3/064 (2013.01); G06F 9/30098 (2013.01); G06F 12/0607 (2013.01); G06F 3/0679 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory controller comprising circuitry for a memory manager to:
identify a low power mode block and a non-low power mode block in a set of functional blocks;
map the low power mode block to a first memory channel associated with a first address of a memory;
map the non-low power mode block to a second memory channel associated with a second address of the memory that is different from the first address of the memory; and
processor circuitry operably coupled to the circuitry for the memory manager, the processor circuitry comprising a processor core, the processor circuitry to disable the second memory channel to establish a low-power communication pipeline between the processor core and the memory via the first memory channel.