US 12,282,377 B2
Hardware-assisted core frequency and voltage scaling in a poll mode idle loop
Pritesh P. Shah, Round Rock, TX (US); Suresh Chemudupati, Austin, TX (US); Alexander Gendler, Haifa (IL); David Hunt, Meelick (IE); Christopher M. Macnamara, Ballyclough (IE); Ofer Nathan, Haifa (IL); Adwait Purandare, Hillsboro, OR (US); and Ankush Varma, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,224.
Prior Publication US 2022/0413591 A1, Dec. 29, 2022
Int. Cl. G06F 1/3287 (2019.01); G06F 1/3228 (2019.01); G06F 1/3296 (2019.01); G06F 9/50 (2006.01)
CPC G06F 1/3287 (2013.01) [G06F 1/3228 (2013.01); G06F 1/3296 (2013.01); G06F 9/5094 (2013.01); Y02D 10/00 (2018.01)] 11 Claims
OG exemplary drawing
 
1. A hardware controller within a core of a processor to adjust power settings of the core, the hardware controller comprising:
telemetry logic to generate telemetry data that indicates an activity state of the core,
wherein the telemetry data includes one or more of (1) a number of branch hits and (2) a number of branch misses;
core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state, wherein the core stall detection logic is to determine the core is in the idle loop state by calculating a branch miss-to-hit ratio over a time period and based on a set of thresholds, wherein the core stall detection logic is to calculate the branch miss-to-hit ratio using a hardware counter and set an increment level and a decrement level for the hardware counter based on the set of thresholds; and
a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.